Computer systems typically use inexpensive and high density dynamic random access memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). DDR DRAMs offer both high performance and low power operation by providing various low power modes. One of these low power modes is known as precharge power down. During precharge power down, all banks are precharged, an on-chip delay locked loop (DLL) can be disabled, an input clock can be turned off, and output buffers can be disabled to significantly reduce power consumption. Precharge power down is relatively quick to exit, and exit time may be speeded up by keeping the DLL running.
It is desirable for memory controllers to support the variety of possible DDR memory devices on the market today. For example, DDR version three (DDR3), DDR version four (DDR4), low power (LP) DDR3 (LPDDR3), LPDDR4, and graphics DDR version five (gDDR5) are all currently available choices. However each different DDR memory device has different sets of mode registers (MRs), may have different numbers of and configurations of memory banks, and may support different low-power modes. Thus it has been difficult to design a single memory controller to support low power modes for all these variations efficiently.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.